{"id":52394,"date":"2026-10-19T10:55:22","date_gmt":"2026-10-19T03:55:22","guid":{"rendered":"https:\/\/saigonbiz.com\/vn\/?p=52394"},"modified":"2026-10-19T11:07:42","modified_gmt":"2026-10-19T04:07:42","slug":"subsystem-cho-kien-truc-pcie-6-0-dat-chung-nhan-tuan-thu-dac-ta-pci-express-ngay-trong-lan-kiem-dinh-dau-tien","status":"publish","type":"post","link":"https:\/\/saigonbiz.com\/vn\/subsystem-cho-kien-truc-pcie-6-0-dat-chung-nhan-tuan-thu-dac-ta-pci-express-ngay-trong-lan-kiem-dinh-dau-tien\/","title":{"rendered":"Subsystem cho ki\u1ebfn tr\u00fac PCIe 6.0 \u0111\u1ea1t ch\u1ee9ng nh\u1eadn tu\u00e2n th\u1ee7 \u0111\u1eb7c t\u1ea3 PCI Express ngay trong l\u1ea7n ki\u1ec3m \u0111\u1ecbnh \u0111\u1ea7u ti\u00ean"},"content":{"rendered":"<p style=\"font-weight: 400\"><strong>Gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con x8 ho\u00e0n ch\u1ec9nh tr\u00ean ti\u1ebfn tr\u00ecnh TSMC N3 kh\u1eb3ng \u0111\u1ecbnh m\u1ee9c \u0111\u1ed9 s\u1eb5n s\u00e0ng c\u1ee7a ng\u00e0nh cho s\u1ea3n xu\u1ea5t h\u00e0ng lo\u1ea1t v\u00e0 gi\u1ea3m thi\u1ec3u r\u1ee7i ro tri\u1ec3n khai cho kh\u00e1ch h\u00e0ng AI\/HPC.\u00a0<\/strong><\/p>\n<p style=\"font-weight: 400\">Cadence (Nasdaq: CDNS) v\u1eeba c\u00f4ng b\u1ed1 r\u1eb1ng c\u00e1c kh\u1ed1i IP PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n d\u00e0nh cho \u0111\u1eb7c t\u1ea3 PCI Express<sup>\u00ae<\/sup> (PCIe<sup>\u00ae<\/sup>) 6.0, \u0111\u01b0\u1ee3c tri\u1ec3n khai tr\u00ean ti\u1ebfn tr\u00ecnh TSMC N3, \u0111\u00e3 \u0111\u1ea1t k\u1ebft qu\u1ea3 th\u00e0nh c\u00f4ng ngay trong l\u1ea7n ki\u1ec3m \u0111\u1ecbnh \u0111\u1ea7u ti\u00ean t\u1ea1i h\u1ed9i th\u1ea3o (compliance workshop) c\u1ee7a PCI-SIG<sup>\u00ae<\/sup> di\u1ec5n ra v\u00e0o cu\u1ed1i th\u00e1ng 7 v\u1eeba qua. \u0110\u00e2y l\u00e0 s\u1ef1 ki\u1ec7n ch\u00ednh th\u1ee9c \u0111\u1ea7u ti\u00ean c\u1ee7a ng\u00e0nh v\u1ec1 ki\u1ec3m \u0111\u1ecbnh tu\u00e2n th\u1ee7 \u0111\u1eb7c t\u1ea3 PCIe 6.0, trong \u0111\u00f3 gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con x8 c\u1ee7a Cadence \u0111\u01b0\u1ee3c th\u1eed nghi\u1ec7m \u1edf t\u1ed1c \u0111\u1ed9 t\u1ed1i \u0111a 64 GT\/s theo \u0111\u00fang \u0111\u1eb7c t\u1ea3 PCIe 6.0.<\/p>\n<p style=\"font-weight: 400\">Gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con (subsystem) ho\u00e0n ch\u1ec9nh c\u1ee7a Cadence, bao g\u1ed3m c\u1ea3 PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n, \u0111\u00e3 v\u01b0\u1ee3t qua to\u00e0n b\u1ed9 c\u00e1c b\u00e0i ki\u1ec3m tra tu\u00e2n th\u1ee7 ch\u00ednh th\u1ee9c c\u1ee7a \u0111\u1eb7c t\u1ea3 PCIe 6.0 v\u00e0 hi\u1ec7n c\u00f3 t\u00ean trong <a href=\"https:\/\/pcisig.com\/developers\/integrators-list?field_version_value%5B%5D=6&amp;combine=cadence\">Danh s\u00e1ch Nh\u00e0 t\u00edch h\u1ee3p (Integrators List)<\/a>c\u1ee7a PCI-SIG.<\/p>\n<p style=\"font-weight: 400\">&#8220;PCI Express l\u00e0 m\u1ed9t chu\u1ea9n k\u1ebft n\u1ed1i m\u1edf r\u1ed9ng (scale-up) thi\u1ebft y\u1ebfu \u0111\u1ed1i v\u1edbi c\u00e1c trung t\u00e2m d\u1eef li\u1ec7u AI\/HPC v\u00e0 c\u00e1c nh\u00e0 m\u00e1y AI. H\u1ec7 th\u1ed1ng con c\u1ee7a Cadence cho \u0111\u1eb7c t\u1ea3 PCIe 6.0 mang l\u1ea1i hi\u1ec7u n\u0103ng h\u00e0ng \u0111\u1ea7u trong ph\u00e2n kh\u00fac, \u0111\u1ed3ng th\u1eddi n\u1eb1m trong nh\u00f3m c\u00f3 m\u1ee9c ti\u00eau th\u1ee5 \u0111i\u1ec7n n\u0103ng th\u1ea5p nh\u1ea5t tr\u00ean th\u1ecb tr\u01b0\u1eddng&#8221;, \u00f4ng Marc Loinaz, Ph\u00f3 Ch\u1ee7 t\u1ecbch ph\u1ee5 tr\u00e1ch Nghi\u00ean c\u1ee9u v\u00e0 Ph\u00e1t tri\u1ec3n PHY hi\u1ec7u n\u0103ng cao, Nh\u00f3m Gi\u1ea3i ph\u00e1p B\u00e1n d\u1eabn (Silicon Solutions Group) t\u1ea1i Cadence, cho bi\u1ebft. &#8220;Th\u00e0nh c\u00f4ng ngay trong l\u1ea7n \u0111\u1ea7u n\u00e0y ch\u1ee9ng th\u1ef1c cho gi\u1ea3i ph\u00e1p PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n ho\u00e0n ch\u1ec9nh c\u1ee7a ch\u00fang t\u00f4i, \u0111\u1ed3ng th\u1eddi mang l\u1ea1i cho kh\u00e1ch h\u00e0ng s\u1ef1 tin t\u01b0\u1edfng r\u1eb1ng c\u00f4ng ngh\u1ec7 c\u1ee7a Cadence c\u00f3 kh\u1ea3 n\u0103ng t\u01b0\u01a1ng t\u00e1c \u0111\u1ea7y \u0111\u1ee7 v\u00e0 \u0111\u00e3 s\u1eb5n s\u00e0ng cho s\u1ea3n xu\u1ea5t&#8221;.<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/saigonbiz.com\/vn\/wp-content\/uploads\/2026\/10\/First-pass-PCIe-6.0-compliance.jpg\" \/><\/p>\n<p>&nbsp;<\/p>\n<p style=\"font-weight: 400\">C\u1ed9t m\u1ed1c n\u00e0y c\u0169ng cho th\u1ea5y t\u1ea7m quan tr\u1ecdng c\u1ee7a vi\u1ec7c h\u1ee3p t\u00e1c s\u1edbm trong h\u1ec7 sinh th\u00e1i nh\u1eb1m \u0111\u01b0a c\u00e1c chu\u1ea9n c\u00f4ng ngh\u1ec7 m\u1edbi ra th\u1ecb tr\u01b0\u1eddng. Trong nhi\u1ec1u th\u00e1ng tr\u01b0\u1edbc th\u1ec1m h\u1ed9i th\u1ea3o ch\u00ednh th\u1ee9c, Cadence \u0111\u00e3 ph\u1ed1i h\u1ee3p ch\u1eb7t ch\u1ebd v\u1edbi PCI-SIG, c\u00e1c nh\u00e0 cung c\u1ea5p thi\u1ebft b\u1ecb ki\u1ec3m \u0111\u1ecbnh v\u00e0 c\u00e1c \u0111\u1ed1i t\u00e1c trong ng\u00e0nh \u0111\u1ec3 ti\u1ebfn h\u00e0nh th\u1eed nghi\u1ec7m kh\u1ea3 n\u0103ng t\u01b0\u01a1ng t\u00e1c, qua \u0111\u00f3 ph\u00e1t hi\u1ec7n v\u00e0 x\u1eed l\u00fd c\u00e1c v\u1ea5n \u0111\u1ec1 ti\u1ec1m \u1ea9n tr\u01b0\u1edbc khi b\u01b0\u1edbc v\u00e0o \u0111\u00e1nh gi\u00e1 ch\u00ednh th\u1ee9c.<\/p>\n<p style=\"font-weight: 400\">&#8220;Khi c\u00f4ng ngh\u1ec7 PCIe 6.0 m\u1edf \u0111\u01b0\u1eddng cho th\u1ebf h\u1ec7 h\u1ec7 th\u1ed1ng AI v\u00e0 \u0111i\u1ec7n to\u00e1n hi\u1ec7u n\u0103ng cao ti\u1ebfp theo, vi\u1ec7c ki\u1ec3m \u0111\u1ecbnh tu\u00e2n th\u1ee7 v\u00e0 t\u01b0\u01a1ng t\u00e1c m\u1ed9t c\u00e1ch nghi\u00eam ng\u1eb7t l\u00e0 y\u1ebfu t\u1ed1 s\u1ed1ng c\u00f2n \u0111\u1ed1i v\u1edbi th\u00e0nh c\u00f4ng c\u1ee7a c\u1ea3 h\u1ec7 sinh th\u00e1i&#8221;, \u00f4ng Brig Asay, T\u1ed5ng Gi\u00e1m \u0111\u1ed1c m\u1ea3ng Trung t\u00e2m D\u1eef li\u1ec7u M\u1ea1ng t\u1ea1i Keysight Technologies, nh\u1eadn \u0111\u1ecbnh. &#8220;Th\u00e0nh t\u1ef1u \u0111\u1ea1t chu\u1ea9n ngay l\u1ea7n \u0111\u1ea7u c\u1ee7a Cadence ph\u1ea3n \u00e1nh c\u1ea3 ch\u1ea5t l\u01b0\u1ee3ng tri\u1ec3n khai h\u1ec7 th\u1ed1ng con PCIe 6.0 l\u1eabn hi\u1ec7u qu\u1ea3 c\u1ee7a quy tr\u00ecnh ki\u1ec3m \u0111\u1ecbnh to\u00e0n di\u1ec7n s\u1eed d\u1ee5ng c\u00e1c gi\u1ea3i ph\u00e1p \u0111o ki\u1ec3m c\u1ee7a Keysight. Ch\u00fang t\u00f4i r\u1ea5t vui \u0111\u01b0\u1ee3c \u0111\u1ed3ng h\u00e0nh c\u00f9ng c\u00e1c doanh nghi\u1ec7p d\u1eabn \u0111\u1ea7u ng\u00e0nh trong vi\u1ec7c \u0111\u1ea9y nhanh qu\u00e1 tr\u00ecnh tri\u1ec3n khai c\u00f4ng ngh\u1ec7 PCIe 6.0 m\u1ed9t c\u00e1ch v\u1eefng ch\u1eafc&#8221;.<\/p>\n<p style=\"font-weight: 400\">&#8220;Cadence l\u00e0 th\u00e0nh vi\u00ean l\u00e2u n\u0103m c\u1ee7a PCI-SIG v\u00e0 \u0111\u00e3 g\u00f3p ph\u1ea7n th\u00fac \u0111\u1ea9y vi\u1ec7c \u1ee9ng d\u1ee5ng c\u00f4ng ngh\u1ec7 PCIe&#8221;, \u00f4ng Al Yanes, Ch\u1ee7 t\u1ecbch PCI-SIG, chia s\u1ebb. &#8220;C\u1ed9t m\u1ed1c tu\u00e2n th\u1ee7 PCIe 6.0 c\u1ee7a Cadence c\u00f3 \u00fd ngh\u0129a \u0111\u1ed1i v\u1edbi ti\u1ebfn tr\u00ecnh ph\u00e1t tri\u1ec3n li\u00ean t\u1ee5c c\u1ee7a ki\u1ebfn tr\u00fac c\u00f4ng ngh\u1ec7 PCIe&#8221;.<\/p>\n<p style=\"font-weight: 400\">C\u00f4ng ngh\u1ec7 PCIe 6.0 \u0111\u00e1p \u1ee9ng nhu c\u1ea7u ng\u00e0y c\u00e0ng l\u1edbn v\u1ec1 k\u1ebft n\u1ed1i b\u0103ng th\u00f4ng cao trong c\u00e1c h\u1ec7 th\u1ed1ng AI v\u00e0 \u0111i\u1ec7n to\u00e1n hi\u1ec7u n\u0103ng cao, n\u01a1i chu\u1ea9n n\u00e0y \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng cho card t\u0103ng t\u1ed1c, giao ti\u1ebfp m\u1ea1ng v\u00e0 thi\u1ebft b\u1ecb l\u01b0u tr\u1eef. Giao ti\u1ebfp n\u00e0y \u0111\u01b0\u1ee3c k\u1ef3 v\u1ecdng s\u1ebd \u0111\u01b0\u1ee3c \u1ee9ng d\u1ee5ng r\u1ed9ng r\u00e3i trong h\u1ea1 t\u1ea7ng trung t\u00e2m d\u1eef li\u1ec7u v\u00e0 AI, sau \u0111\u00f3 m\u1edf r\u1ed9ng sang c\u00e1c h\u1ec7 th\u1ed1ng \u00f4 t\u00f4 v\u00e0 doanh nghi\u1ec7p khi h\u1ec7 sinh th\u00e1i d\u1ea7n ho\u00e0n thi\u1ec7n.<\/p>\n<p style=\"font-weight: 400\">&#8220;Positron AI \u0111\u00e3 c\u1ea5p ph\u00e9p s\u1eed d\u1ee5ng IP SerDes c\u1ee7a Cadence cho \u0111\u1eb7c t\u1ea3 PCIe 6.0 trong chip t\u0103ng t\u1ed1c suy lu\u1eadn AI c\u1ee7a ch\u00fang t\u00f4i&#8221;, \u00f4ng Thomas Sohmers, Gi\u00e1m \u0111\u1ed1c C\u00f4ng ngh\u1ec7 t\u1ea1i Positron AI, cho bi\u1ebft. &#8220;H\u1ec7 th\u1ed1ng con PCIe 6.0 ho\u00e0n ch\u1ec9nh \u0111\u00e3 \u0111\u01b0\u1ee3c hi\u1ec7n th\u1ef1c h\u00f3a tr\u00ean silicon c\u00f9ng quy tr\u00ecnh ki\u1ec3m \u0111\u1ecbnh kh\u1ea3 n\u0103ng t\u01b0\u01a1ng t\u00e1c ch\u1eb7t ch\u1ebd c\u1ee7a Cadence gi\u00fap ch\u00fang t\u00f4i y\u00ean t\u00e2m r\u1eb1ng giao ti\u1ebfp PCIe 6.0 c\u1ee7a m\u00ecnh s\u1ebd \u0111\u00e1p \u1ee9ng \u0111\u01b0\u1ee3c y\u00eau c\u1ea7u k\u1ebft n\u1ed1i b\u0103ng th\u00f4ng cao c\u1ee7a c\u00e1c t\u00e1c v\u1ee5 transformer&#8221;.<\/p>\n<p style=\"font-weight: 400\">C\u00e1c \u0111\u1eb7c \u0111i\u1ec3m ch\u00ednh trong gi\u1ea3i ph\u00e1p c\u00f4ng ngh\u1ec7 PCIe 6.0 c\u1ee7a Cadence bao g\u1ed3m:<\/p>\n<ul>\n<li>Gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con ho\u00e0n ch\u1ec9nh v\u1edbi PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n \u0111\u00e3 \u0111\u01b0\u1ee3c hi\u1ec7n th\u1ef1c h\u00f3a tr\u00ean silicon<\/li>\n<li>C\u00e2n b\u1eb1ng t\u00edn hi\u1ec7u d\u1ef1a tr\u00ean ADC v\u00e0 DSP<\/li>\n<li>Ho\u1ea1t \u0111\u1ed9ng SerDes \u0111\u01b0\u1ee3c t\u1ed1i \u01b0u b\u1eb1ng ph\u1ea7n m\u1ec1m nh\u00fang (firmware)<\/li>\n<li>T\u00ednh linh ho\u1ea1t v\u00e0 kh\u1ea3 n\u0103ng h\u1ed7 tr\u1ee3 \u0111a giao th\u1ee9c<\/li>\n<li>T\u1ed1i \u01b0u cho m\u1ee9c ti\u00eau th\u1ee5 \u0111i\u1ec7n n\u0103ng th\u1ea5p, bao g\u1ed3m h\u1ed7 tr\u1ee3 c\u00e1c th\u00f4ng b\u00e1o thay \u0111\u1ed5i k\u1ef9 thu\u1eadt (ECN) m\u1edbi nh\u1ea5t c\u1ee7a PCI-SIG<\/li>\n<li>Ch\u1ee9ng nh\u1eadn cho c\u1ea5u h\u00ecnh x8 tr\u00ean ti\u1ebfn tr\u00ecnh TSMC N3<\/li>\n<\/ul>\n<p style=\"font-weight: 400\">PCI-SIG li\u00ean t\u1ee5c ph\u00e1t tri\u1ec3n chu\u1ea9n PCIe nh\u1eb1m \u0111\u00e1p \u1ee9ng nhu c\u1ea7u c\u1ee7a c\u00e1c t\u00e1c v\u1ee5 HPC v\u00e0 AI ti\u00ean ti\u1ebfn. Cadence hi\u1ec7n cung c\u1ea5p danh m\u1ee5c gi\u1ea3i ph\u00e1p c\u00f4ng ngh\u1ec7 PCIe r\u1ed9ng kh\u1eafp, l\u00ean \u0111\u1ebfn \u0111\u1eb7c t\u1ea3 PCIe 7.0.<\/p>\n<p style=\"font-weight: 400\">Gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con ho\u00e0n ch\u1ec9nh c\u1ee7a Cadence cho c\u00f4ng ngh\u1ec7 PCIe 6.0, bao g\u1ed3m PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n, \u0111\u00e3 s\u1eb5n s\u00e0ng \u0111\u1ec3 c\u00e1c nh\u00e0 cung c\u1ea5p SoC t\u00edch h\u1ee3p v\u00e0o thi\u1ebft k\u1ebf. \u0110\u1ec3 bi\u1ebft th\u00eam th\u00f4ng tin v\u1ec1 IP c\u1ee7a Cadence d\u00e0nh cho c\u00f4ng ngh\u1ec7 PCIe 6.0, vui l\u00f2ng truy c\u1eadp <a href=\"https:\/\/www.cadence.com\/en_US\/home\/tools\/silicon-solutions\/design-ip\/pcie-and-compute-express-link\/phy-for-pcie-and-cxl.html\">trang s\u1ea3n ph\u1ea9m PHY cho PCIe 6.0 v\u00e0 CXL c\u1ee7a Cadence<\/a> ho\u1eb7c t\u1ea3i v\u1ec1 <a href=\"https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/en_US\/documents\/tools\/silicon-solutions\/design-ip\/design-ip-br.pdf\">t\u00e0i li\u1ec7u gi\u1edbi thi\u1ec7u Design IP<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Gi\u1ea3i ph\u00e1p h\u1ec7 th\u1ed1ng con x8 ho\u00e0n ch\u1ec9nh tr\u00ean ti\u1ebfn tr\u00ecnh TSMC N3 kh\u1eb3ng \u0111\u1ecbnh m\u1ee9c \u0111\u1ed9 s\u1eb5n s\u00e0ng c\u1ee7a ng\u00e0nh cho s\u1ea3n xu\u1ea5t h\u00e0ng lo\u1ea1t v\u00e0 gi\u1ea3m thi\u1ec3u r\u1ee7i ro tri\u1ec3n khai cho kh\u00e1ch h\u00e0ng AI\/HPC.\u00a0 Cadence (Nasdaq: CDNS) v\u1eeba c\u00f4ng b\u1ed1 r\u1eb1ng c\u00e1c kh\u1ed1i IP PHY v\u00e0 b\u1ed9 \u0111i\u1ec1u khi\u1ec3n d\u00e0nh cho \u0111\u1eb7c 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